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» Floorplanning in Modern FPGAs
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FPGA
1997
ACM
130views FPGA» more  FPGA 1997»
13 years 9 months ago
Synthesis and Floorplanning for Large Hierarchical FPGAs
Helena Krupnova, Christian Rabedaoro, Gabriele Sau...
ASPDAC
2008
ACM
98views Hardware» more  ASPDAC 2008»
13 years 7 months ago
A unified methodology for power supply noise reduction in modern microarchitecture design
In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates ...
Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Le...
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 2 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
FPL
2007
Springer
133views Hardware» more  FPL 2007»
13 years 11 months ago
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guille...
COCOON
2005
Springer
13 years 11 months ago
A Theoretical Upper Bound for IP-Based Floorplanning
Floorplan is a crucial estimation task in the modern layout design of systems on chips. The paper presents a novel theoretical upper bound for slicing floorplans with soft modules...
Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei ...