161 search results - page 1 / 33 » Floorplanning with Datapath Optimization |
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
IJES
2008
13 years 4 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...