Sciweavers

34 search results - page 1 / 7
» Flow regulation for on-chip communication
Sort
View
ICPP
2005
IEEE
13 years 10 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 8 months ago
Efficient On-Chip Communications for Data-Flow IPs
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their ion in a system on chip. We abstract the communication behaviour of the data flow IP so a...
Antoine Fraboulet, Tanguy Risset
ICCD
2002
IEEE
109views Hardware» more  ICCD 2002»
14 years 1 months ago
Physical Planning Of On-Chip Interconnect Architectures
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand fo...
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 8 months ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
MASCOTS
2008
13 years 6 months ago
On the Stability of Best Effort Flow Control Mechanisms in On-Chip Architectures
In this paper we present a centralized flow control scheme in NoCs in the presence of both elastic and streaming flow traffic paradigms. We model the desired Best Effort (BE) sour...
Mohammad Sadegh Talebi, Ahmad Khonsari