67 search results - page 2 / 14 » Formal Verification of Digital Circuits Using Symbolic Terna... |
FDL
2003
IEEE
13 years 11 months ago
2003
IEEE
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
FDL
2006
IEEE
13 years 9 months ago
2006
IEEE
In this work, an approach to the `verification-oriented' modeling of the analog parts' behavior of mixed-signal circuits is presented. Starting from a continuous-time, c...
FMCAD
2007
Springer
13 years 9 months ago
2007
Springer
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
IJCAI
2003
13 years 7 months ago
2003
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...