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CAV
1990
Springer
114views Hardware» more  CAV 1990»
13 years 9 months ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger
VLSID
1997
IEEE
173views VLSI» more  VLSID 1997»
13 years 10 months ago
Formal Verification of Digital Systems
Gitanjali Swamy
EUROMICRO
1996
IEEE
13 years 10 months ago
A Graph Rewriting Approach for Transformational Design of Digital Systems
Transformational design integrates design and verification. It combines "correctness by construciion" and design creativity by the use ofpre-proven behaviour preserving ...
Corrie Huijs
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
13 years 9 months ago
Formal Refinement and Model Checking of an Echo Cancellation Unit
This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML sta...
Alexander Krupp, Wolfgang Müller 0003, Ian Ol...