176 search results - page 4 / 36 » Formal Verification of Gate-Level Computer Systems |
JCP
2008
13 years 6 months ago
2008
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
ISORC
2000
IEEE
13 years 9 months ago
2000
IEEE
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
BIRTHDAY
2007
Springer
13 years 10 months ago
2007
Springer
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...