12 search results - page 1 / 3 » Formal verification of pipeline conflicts in RISC processors |
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...
TODAES
1998
13 years 4 months ago
1998
Abstract State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a ...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...