Sciweavers

227 search results - page 2 / 46
» Formal verification of systems with an unlimited number of c...
Sort
View
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
13 years 9 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu
FDL
2007
IEEE
13 years 9 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
SIGSOFT
2005
ACM
14 years 6 months ago
Towards a unified formal model for supporting mechanisms of dynamic component update
The continuous requirements of evolving a delivered software system and the rising cost of shutting down a running software system are forcing researchers and practitioners to fin...
Junrong Shen, Xi Sun, Gang Huang, Wenpin Jiao, Yan...
FDL
2004
IEEE
13 years 9 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
COOPIS
2004
IEEE
13 years 9 months ago
Checking Asynchronously Communicating Components Using Symbolic Transition Systems
Abstract. Explicit behavioural interface description languages (BIDLs, protocols) are now recognized as a mandatory feature of component languages in order to address component reu...
Olivier Maréchal, Pascal Poizat, Jean-Claud...