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» Framework for Fault Analysis and Test Generation in DRAMs
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DATE
2005
IEEE
96views Hardware» more  DATE 2005»
13 years 11 months ago
Framework for Fault Analysis and Test Generation in DRAMs
Abstract: With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory t...
Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. v...
DATE
2006
IEEE
75views Hardware» more  DATE 2006»
13 years 11 months ago
Space of DRAM fault models and corresponding testing
Abstract: DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of faul...
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
MTDT
2003
IEEE
124views Hardware» more  MTDT 2003»
13 years 10 months ago
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
Zaid Al-Ars, A. J. van de Goor
ATS
2003
IEEE
126views Hardware» more  ATS 2003»
13 years 10 months ago
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...
Zaid Al-Ars, A. J. van de Goor
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
13 years 10 months ago
Modeling Techniques and Tests for Partial Faults in Memory Devices
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
Zaid Al-Ars, A. J. van de Goor