348 search results - page 69 / 70 » From monotone inequalities to Model Predictive Control |
CODES
2009
IEEE
13 years 10 months ago
2009
IEEE
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
AGENTS
1997
Springer
13 years 10 months ago
1997
Springer
We have been developing Rogue, an architecture that integrates high-level planning with a low-level executing robotic agent. Rogue is designed as the oce gofer task planner for X...
NSDI
2004
13 years 7 months ago
2004
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
HPDC
2009
IEEE
14 years 15 days ago
2009
IEEE
This paper explores the feasibility of a cost-efficient storage architecture that offers the reliability and access performance characteristics of a high-end system. This architec...
CF
2009
ACM
14 years 8 days ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...