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ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
13 years 9 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
ISPD
2005
ACM
153views Hardware» more  ISPD 2005»
13 years 11 months ago
Evaluation of placer suboptimality via zero-change netlist transformations
In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from a placer, we formal...
Andrew B. Kahng, Sherief Reda
DAC
2012
ACM
11 years 7 months ago
A metric for layout-friendly microarchitecture optimization in high-level synthesis
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Jason Cong, Bin Liu
ISCAS
2002
IEEE
89views Hardware» more  ISCAS 2002»
13 years 10 months ago
Seamless switching of scalable video bitstreams for efficient streaming
—Efficient adaptation to channel bandwidth is broadly required for effective streaming video over the Internet. To address this requirement, a novel seamless switching scheme amo...
Xiaoyan Sun, Feng Wu, Shipeng Li, Wen Gao, Ya-Qin ...
CCS
2011
ACM
12 years 5 months ago
On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs
Over the last two decades FPGAs have become central components for many advanced digital systems, e.g., video signal processing, network routers, data acquisition and military sys...
Amir Moradi, Alessandro Barenghi, Timo Kasper, Chr...