8 search results - page 1 / 2 » Full Sensitivity and Test Generation for Multiple-Valued Log... |
ISMVL
1994
IEEE
13 years 9 months ago
1994
IEEE
ET
2010
13 years 3 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...