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ISMVL
1994
IEEE
94views Hardware» more  ISMVL 1994»
14 years 2 months ago
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits
Elena Dubrova, Dilian Gurov, Jon C. Muzio
ET
2010
98views more  ET 2010»
13 years 9 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
14 years 3 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
14 years 3 months ago
Charge sharing fault analysis and testing for CMOS domino logic circuits
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh...
DAC
1994
ACM
14 years 2 months ago
Dynamic Search-Space Pruning Techniques in Path Sensitization
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
João P. Marques Silva, Karem A. Sakallah