26 search results - page 1 / 6 » Full-Chip Multilevel Routing for Power and Signal Integrity |
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
In this work, we propose an enhanced design method for filterless class-D audio amplifier based on multilevel architecture. The multilevel technique consists of a multilevel conve...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...