192 search results - page 2 / 39 » Functional Scan Chain Testing |
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
TCAD
1998
13 years 4 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...