123 search results - page 3 / 25 » Functional Test Generation for FSMs by Fault Extraction |
VTS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
TODAES
1998
13 years 5 months ago
1998
