21 search results - page 1 / 5 » Functional Verification for SystemC Descriptions Using Const... |
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
SIES
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
DT
2006
13 years 5 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— This paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. Arithmet...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...