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ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
13 years 11 months ago
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
Yu Zhou, Danil Sokolov, Alexandre Yakovlev
DAGSTUHL
2003
13 years 6 months ago
Embedding a Hardware Description Language in Template Haskell
Abstract. Hydra is a domain-specific language for designing digital circuits, which is implemented by embedding within Haskell. Many features required for hardware specification ...
John T. O'Donnell
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
13 years 11 months ago
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of ion. A possible sol...
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide P...
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
14 years 2 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch
ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
13 years 9 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar