Sciweavers

33 search results - page 4 / 7
» Functional test generation using property decompositions for...
Sort
View
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
14 years 6 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
MICRO
2002
IEEE
124views Hardware» more  MICRO 2002»
13 years 10 months ago
Optimizing pipelines for power and performance
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
Viji Srinivasan, David Brooks, Michael Gschwind, P...
TVLSI
2008
152views more  TVLSI 2008»
13 years 5 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
JAVACARD
2000
13 years 9 months ago
Automatic Test Generation for Java-Card Applets
: Open-cards have introduced a new life cycle for smart card embedded applications. In the case of Java Card, they have raised the problem of embedded object-oriented applet valida...
Hugues Martin, Lydie du Bousquet
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 9 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...