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TC
2010
13 years 3 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
13 years 11 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
13 years 10 months ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
DAC
2009
ACM
13 years 9 months ago
Non-cycle-accurate sequential equivalence checking
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol...
HPDC
2010
IEEE
13 years 6 months ago
Exploring application and infrastructure adaptation on hybrid grid-cloud infrastructure
Clouds are emerging as an important class of distributed computational resources and are quickly becoming an integral part of production computational infrastructures. An importan...
Hyunjoo Kim, Yaakoub El Khamra, Shantenu Jha, Mani...