32 search results - page 1 / 7 » Gate Level Statistical Simulation Based on Parameterized Mod... |
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires at...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...