44 search results - page 9 / 9 » Gate delay calculation considering the crosstalk capacitance... |
IOLTS
2003
IEEE
13 years 10 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
GLVLSI
2000
IEEE
13 years 10 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ISQED
2009
IEEE
14 years 10 days ago
2009
IEEE
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...