CMOS system-on-a-chip voltage scaling beyond 50nm

† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected local and global clock rates for high performance processors. Physical short-channel MOSFET models that consider high-field effects, threshold voltage roll-off and subthreshold swing roll-up are employed in tandem with stochastic interconnect distributions to calculate optimal supply voltage, threshold voltage and gate sizes that minimize total CMOS power dissipation by exploiting trade-offs between saturation drive current and subthreshold leakage current and between device size and wiring capacitance. CMOS power dissipation at its lower limit, increases exponentially with clock frequency imposing limits on performance set by heat removal. Heat removal constraints at high local clock rates, limiting the average wire length and device size within a local zone of synchrony, or macrocell, in a short-wire cellular ...

• Type: Conference
• Year: 2000
• Where: GLVLSI
• Authors: Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
• Keywords: CMOS Energy Dissipation, CMOS Power Dissipation, GLVLSI 2000, Subthreshold Leakage Current, VLSI