4 search results - page 1 / 1 » Gate sizing and buffer insertion for optimizing performance ... |
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...