18 search results - page 1 / 4 » Gate sizing using incremental parameterized statistical timi... |
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...