38 search results - page 3 / 8 » Gate sizing with controlled displacement |
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
APCSAC
2004
IEEE
13 years 9 months ago
2004
IEEE
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
VTS
2005
IEEE
13 years 11 months ago
2005
IEEE
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
ITC
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...