8 search results - page 1 / 2 » Gate-size selection for standard cell libraries |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...