24 search results - page 1 / 5 » Gated Clock Routing Minimizing the Switched Capacitance |
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching...