24 search results - page 2 / 5 » Gated Clock Routing Minimizing the Switched Capacitance |
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...