1862 search results - page 3 / 373 » General Architecture for Hardware Implementation of Genetic ... |
WOB
2004
13 years 6 months ago
2004
ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
IJON
2007
13 years 5 months ago
2007
—This paper presents a novel genetic algorithm, termed the Optimum Individual Monogenetic Algorithm (OIMGA) and describes its hardware implementation. As the monogenetic strategy...
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
13 years 9 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
FCCM
2009
IEEE
13 years 9 months ago
2009
IEEE
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
ATS
2001
IEEE
13 years 9 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...