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CODES
2006
IEEE
13 years 11 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
CODES
2006
IEEE
13 years 11 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
CODES
1999
IEEE
13 years 10 months ago
Co-design tool construction using APICES
In this paper, we present our approach to automate the development process of co-design tools. We demonstrate with a non-trivial real world example how we can accelerate the tool ...
Ansgar Bredenfeld
CODES
2007
IEEE
14 years 3 days ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
13 years 11 months ago
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri