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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 2 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
IEAAIE
1999
Springer
13 years 10 months ago
New Directions in Debugging Hardware Designs
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
Franz Wotawa
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
13 years 10 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
EH
1999
IEEE
351views Hardware» more  EH 1999»
13 years 10 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
IJISTA
2007
119views more  IJISTA 2007»
13 years 5 months ago
Online modelling based on Genetic Programming
: Genetic Programming (GP), a heuristic optimisation technique based on the theory of Genetic Algorithms (GAs), is a method successfully used to identify non-linear model structure...
Stephan M. Winkler, Hajrudin Efendic, Luigi del Re...