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» Geometric Algorithms for Private-Cache Chip Multiprocessors ...
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ICPP
2009
IEEE
14 years 2 days ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 5 months ago
A Single-Chip Multiprocessor for Smart Terminals
dards, language abstraction continues unabatrpretation of such high-level abstract languages requires high performance. The MP98 low-power, high-performance microprocessor architec...
Masato Edahiro, Satoshi Matsushita, Masakazu Yamas...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
14 years 5 days ago
Process variation aware thread mapping for Chip Multiprocessors
Abstract—With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiproce...
Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut ...
DAGSTUHL
2007
13 years 6 months ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
John O'Donnell