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» Getting High-Performance Silicon from System-Level Design
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ICMCS
2005
IEEE
133views Multimedia» more  ICMCS 2005»
13 years 10 months ago
Architecture for area-efficient 2-D transform in H.264/AVC
As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevita...
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei ...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 5 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 8 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
ICCD
2006
IEEE
140views Hardware» more  ICCD 2006»
14 years 1 months ago
Clustering-Based Microcode Compression
Abstract— Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to...
Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, ...
ICCD
2006
IEEE
115views Hardware» more  ICCD 2006»
14 years 1 months ago
Long-term Performance Bottleneck Analysis and Prediction
— Identifying performance bottlenecks is important for microarchitects and application developers to produce high performance microprocessor designs and application software. Man...
Fei Gao, Suleyman Sair