41 search results - page 2 / 9 » Glitch Analysis and Reduction in Register Transfer Level |
ISLPED
2000
ACM
13 years 9 months ago
2000
ACM
We introduce an energy consumption analysis of complex digital systems through a case study of ARM7TDMI RISC processor by using a new energy measurement technique. We developed a ...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
TCAD
2008
13 years 5 months ago
2008
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
TCAD
2011
12 years 12 months ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...