2 search results - page 1 / 1 » GlitchLess: Dynamic Power Minimization in FPGAs Through Edge... |
TVLSI
2008
13 years 4 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...