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    CODES
    2005
    IEEE
    122views Software Engineering» more  CODES 2005»
    DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
    13 years 11 months ago
    DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
    Download  home.rcs.ei.tum.de
    We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
    Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
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    CODES
    2007
    IEEE
    110views Software Engineering» more  CODES 2007»
    Three-dimensional multiprocessor system-on-chip thermal optimization
    13 years 11 months ago
    Three-dimensional multiprocessor system-on-chip thermal optimization
    Download  post.queensu.ca
    3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
    Chong Sun, Li Shang, Robert P. Dick
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