27 search results - page 2 / 6 » Hardware Synthesis for Asynchronous Communications Mechanism... |
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
CHARME
2001
Springer
13 years 9 months ago
2001
Springer
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
ACSD
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper we introduce the notion of weak endochrony, which extends to a synchronous setting the classical theory of Mazurkiewicz traces. The notion is useful in the synthesis ...