Sciweavers

55 search results - page 10 / 11
» Hardware and Petri Nets: Application to Asynchronous Circuit...
Sort
View
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
13 years 11 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
13 years 11 months ago
Energy-efficient FPGA interconnect design
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size...
Maurice Meijer, Rohini Krishnan, Martijn T. Benneb...
PIMRC
2008
IEEE
14 years 23 hour ago
Radio-Triggered Wake-ups with Addressing Capabilities for extremely low power sensor network applications
Sensor network applications are generally characterized by long idle durations and intermittent communication patterns. The traffic loads are typically so low that overall idle d...
Junaid Ansari, Dmitry Pankin, Petri Mähö...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
13 years 11 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 10 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...