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ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
13 years 9 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
ATVA
2006
Springer
131views Hardware» more  ATVA 2006»
13 years 9 months ago
Timed Unfoldings for Networks of Timed Automata
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
DAC
2007
ACM
14 years 6 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
ISPD
2003
ACM
89views Hardware» more  ISPD 2003»
13 years 10 months ago
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
Andrew B. Kahng, Xu Xu
SENSYS
2009
ACM
13 years 12 months ago
Run time assurance of application-level requirements in wireless sensor networks
Continuous and reliable operation of WSNs is notoriously difficult to guarantee due to hardware degradation and environmental changes. In this paper, we propose and demonstrate a ...
Jingyuan Li, Yafeng Wu, Krasimira Kapitanova, John...