48 search results - page 5 / 10 » Hardware architecture design of an H.264 AVC video codec |
VTC
2010
IEEE
13 years 4 months ago
2010
IEEE
— In this contribution we propose a robust H.264 coded wireless video transmission scheme using iteratively decoded self-concatenated convolutional coding (SECCC). The proposed S...
DSD
2007
IEEE
14 years 2 days ago
2007
IEEE
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
ICMCS
2006
IEEE
13 years 11 months ago
2006
IEEE
We propose a high performance architecture for fractional motion estimation and Lagrange mode decision in H.264/AVC. Instead of time-consuming fractional-pixel interpolation and s...
AHS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is d...
VLSISP
2011
13 years 20 days ago
2011
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...