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SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
13 years 11 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
13 years 12 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
ATVA
2007
Springer
226views Hardware» more  ATVA 2007»
14 years 14 days ago
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
David Walter, Scott Little, Chris J. Myers
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
14 years 7 days ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...