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» Heterogeneous systems on chip and systems in package
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ASPLOS
2009
ACM
14 years 6 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
HOTI
2008
IEEE
14 years 6 days ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
SIGGRAPH
2000
ACM
13 years 10 months ago
The WarpEngine: an architecture for the post-polygonal age
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
Voicu Popescu, John G. Eyles, Anselmo Lastra, Josh...
DAC
1997
ACM
13 years 10 months ago
Electronic Component Information Exchange (ECIX)
A number of industry trends are shaping the requirements for IC and electronic equipment design. The density and complexity of circuit technologies have increased to a point where...
Donald R. Cottrell
BMCBI
2011
12 years 9 months ago
PeakRanger: A cloud-enabled peak caller for ChIP-seq data
Background: Chromatin immunoprecipitation (ChIP), coupled with massively parallel short-read sequencing (seq) is used to probe chromatin dynamics. Although there are many algorith...
Xin Feng, Robert Grossman, Lincoln Stein