41 search results - page 3 / 9 » Hierarchical Checking of Multiprocessors Using Watchdog Proc... |
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...
ETS
2010
IEEE
13 years 6 months ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
CHARME
2001
Springer
13 years 9 months ago
2001
Springer
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
JTRES
2010
ACM
13 years 6 months ago
2010
ACM
Chip-multiprocessors offer increased processing power at a low cost. However, in order to use them for real-time systems, tasks have to be scheduled efficiently and predictably. I...