238 search results - page 3 / 48 » Hierarchical Interconnect Circuit Models |
ICCAD
1993
IEEE
13 years 10 months ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
ICCAD
1999
IEEE
13 years 10 months ago
1999
IEEE
Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtain...
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
ASPDAC
1999
ACM
13 years 10 months ago
1999
ACM
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...