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» Hierarchical Krylov subspace reduced order modeling of large...
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ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
Duo Li, Sheldon X.-D. Tan
VLSID
2002
IEEE
124views VLSI» more  VLSID 2002»
14 years 5 months ago
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
13 years 11 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
DAC
2003
ACM
14 years 6 months ago
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEM
In this paper we propose a method for generating reduced models for a class of nonlinear dynamical systems, based on truncated balanced realization (TBR) algorithm and a recently ...
Dmitry Vasilyev, Michal Rewienski, Jacob White
ICCAD
2005
IEEE
101views Hardware» more  ICCAD 2005»
14 years 2 months ago
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variat
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
Xin Li, Peng Li, Lawrence T. Pileggi