64 search results - page 11 / 13 » Hierarchical Optimization of Asynchronous Circuits |
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...