64 search results - page 12 / 13 » Hierarchical Optimization of Asynchronous Circuits |
ACSD
2003
IEEE
13 years 8 months ago
2003
IEEE
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
GECCO
2004
Springer
13 years 10 months ago
2004
Springer
Genetic algorithms require relatively large computation time to solve optimization problems, especially in VLSI CAD such as module placement. Therefore, island-based parallel GAs a...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
ICCCN
2007
IEEE
13 years 11 months ago
2007
IEEE
—Multimedia requirements of the 1990’s drove wired and optical network architects to reconsider the inefficiencies of packet switching and consider long proven methods such as...
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...