59 search results - page 1 / 12 » Hierarchical Test Generation with Built-In Fault Diagnosis |
ATS
1996
IEEE
13 years 9 months ago
1996
IEEE
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
IOLTS
2006
IEEE
13 years 10 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...