8 search results - page 1 / 2 » Hierarchical buffered routing tree generation |
TCAD
2002
13 years 4 months ago
2002
Abstract--This paper presents a solution to the problem of performance-driven buffered routing tree generation for VLSI circuits. Using a novel bottom-up construction algorithm and...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algor...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...